AN4035 datasheet(21/42 Pages) STMICROELECTRONICS

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AN4035

On-Chip Emulation (OnCE)

Doc ID 022669 Rev 2

21/41

entering debug mode, the OCR[DR] bit should be cleared leaving the OCR[WKUP] bit set.

OCR[FDB] should also then be set to enable recognition of software breakpoints.

The steps required for entering debug mode during reset assuming the OnCE TAP

controller has been enabled are listed below:

Assert RESET.

Set the OCR[DR] and OCR[WKUP] bits.

De-assert RESET.

Verify debug mode via the DEBUG bit in the OnCE status register.

Clear the OCR[DR] bit while leaving OCR[WKUP] set and set OCR[FDB].

3.6

Enabling external debug mode and other initialization

Before enabling external debug mode, the CPU should be placed into debug mode via the

method outlined in the previous section.

The external tool should then write the DBCR0[EDM] bit to enable external debug mode.

Note that the first write to DBCR0 only affects the EDM bit. All other bits in that register

require DBCR0[EDM] to be set prior to writing them. After enabling external debug mode,

the DBSR status bits should be cleared by writing 0xFFFFFFFF to DBSR. The register

definition of DBSR is shown in Figure 16.

Figure 16.

Debug Status Register (DBSR)

3.7

CPU Status and Control Scan Chain Register (CPUSCR)

CPU information is accessible via the OnCE module through a single scan chain register

named the CPUSCR. The CPUSCR provides access to this CPU information and a

mechanism for an external tool to set the CPU to a desired state before exiting debug mode.

The CPUSCR also provides the ability to access register and memory contents. Figure 3-13

shows the CPUSCR. Once debug mode has been entered, it is required to scan in and

update the CPUSCR prior to exiting debug mode or single stepping. Access to the CPUSCR

is controlled by the OCMD.

01234

56789

IDE

UDE

MRR

ICMP

BRT

IRPT

TRAP

IAC1

IAC2

IAC3

IAC4

DAC

Reset

00010

0000000

RET

0000

DEVT

DEV

DCNT

CIRPT

CRET

CNT

1RG

Reset

00000

0000000

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