AN4035 datasheet(23/42 Pages) STMICROELECTRONICS

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AN4035

On-Chip Emulation (OnCE)

Doc ID 022669 Rev 2

23/41

3.7.2

Control State Register (CTL)

The control state register (CTL) stores the value of certain internal CPU state variables

before debug mode is entered. Figure 18 shows the CTL register.

Figure 18.

Control State Register (CTL)

The “*” in the CTL register represents internal processor state bits that should be restored to

the value they held when debug mode was entered prior to exiting debug mode. If a single

step is executing an instruction that is in the normal instruction flow of the program that was

running when debug mode was entered, these bits should be restored. If a single step is

executing an instruction outside the normal instruction flow, these bits should be cleared to

zero.

The PCOFST field indicates whether the value in the PC portion of the CPUSCR must be

adjusted prior to exiting debug mode. Due to the pipelined nature of the CPU, the PC value

must be backed-up under certain circumstances. The PCOFST field specifies the value to

be subtracted from the PC value when debug mode was entered. This PC value should be

adjusted according to PCOFST prior to exit from debug mode if continuation of the normal

instruction stream is desired. In the event that PCOFST is non-zero, the IR should be

loaded with a nop instruction instead of the value in the IR when debug mode was entered.

Below are the possible values and meanings of the PCOFST field:

●

0000—No correction required.

●

0001—Subtract 0x04 from PC.

●

0010—Subtract 0x08 from PC.

●

0011—Subtract 0x0C from PC.

●

0100—Subtract 0x10 from PC.

●

0101—Subtract 0x14 from PC.

All other encodings are reserved.

After entering debug mode, the PCINV field overrides the PCOFST field and indicates that

values in the PC and IR are invalid. Exiting debug mode with these PC and IR values have

unpredictable results.

No error condition exists.

Error condition exists. PC and IR are corrupt.

The FFRA control bit causes the contents of WBBR to be used as the rA (rS for logical and

shift operations) operand value of the first instruction to be executed when exiting debug

mode or the instruction to be single stepped. This allows the external tool to update CPU

registers and memory. rA and rS are instruction syntax used to identify a source GPR.

No action.

Contents of WBBR used as rA (rS for logical and shift operations) operand value.

The IRStat0-9 bits provide status information to the external tool. The IRStat8 bit indicates

that the instruction in the IR is a VLE or non-VLE instruction. For MPC5500 devices without

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