UM0434 datasheet(31/390 Pages) STMICROELECTRONICS

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e200z3 core complex overview

UM0434

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Each interrupt has an associated interrupt vector address, obtained by concatenating

IVPR[32–47] with the address index in the associated IVOR (that is, IVPR[32–

47]||IVOR

n[48–59] || 0b0000). The resulting address is that of the instruction to be

executed when that interrupt occurs. IVPR and IVOR values are indeterminate on reset and

must be initialized by the system software using mtspr.

Table 4 lists IVOR registers

implemented on the e200z3 core and the associated interrupts.

3.6

Microarchitecture summary

The e200z3 processor has a four-stage pipeline for instruction execution.

Instruction fetch

Instruction decode/register file read/effective address calculation

Execute/memory access

These stages are pipelined, allowing single-clock instruction throughput for most

instructions.

DEAR

Data exception address register—Contains the address that was referenced by a load,

store, or cache management instruction that caused an alignment, data TLB miss, or

data storage interrupt.

IVPR

IVORs

Together, IVPR[32–47] || IVOR

n [48–59] || 0b0000 define the address of an interrupt-

processing routine. See <Cross Refs>Table 5 and <Cross Refs>6, “Interrupts and

exceptions,” for more information.

Table 5.

Exceptions and conditions

IVORn

Interrupt type

IVORn

Interrupt type

None(1)

Vector to [

p_rstbase[0:19]]||0xFFC.

System reset (not an interrupt)

Decrementer

0(2)

Autovectored external and critical input interrupts use this IVOR.

Vectored interrupts supply an interrupt vector offset directly.

Critical input

Fixed-interval timer

Machine check

Watchdog timer

Data storage

Data TLB error

Instruction storage

Instruction TLB error

External input

Debug

Alignment

6–31

Reserved

Program

SPE unavailable

Floating-point unavailable

SPE data exception

System call

SPE round exception

APU unavailable

Table 4.

Interrupt registers (continued)

Description

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