UM0434 datasheet(39/390 Pages) STMICROELECTRONICS

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UM0434

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User-level registers, which are accessible to all software with either user or supervisor

privileges:

–

General-purpose registers (GPRs). Thirty-two 64-bit GPRs (GPR0–GPR31) serve

as data source or destination registers for integer instructions and provide data to

generate addresses. PowerPC Book E instructions affect only the lower 32 bits of

the GPRs. SPE APU instructions operate on the entire 64-bit register.

–

Condition register (CR). Eight 4-bit fields, CR0–CR7, reflect results of certain

arithmetic operations and provide a mechanism for testing and branching.

The remaining user-level registers are SPRs. In the PowerPC architecture, the mtspr

and mfspr instructions are for accessing SPRs.

–

Integer exception register (XER). Indicates overflow and carries for integer

operations.

–

Link register (LR). Provides the branch target address for the branch conditional to

link register (bclr

, bclrl) instructions and holds the address of the instruction that

follows a branch and link instruction, typically for linking to subroutines.

–

Count register (CTR). Holds a loop count that can be decremented during

execution of appropriately coded branch instructions. CTR also provides the

branch target address for the branch conditional to count register (bcctr

, bcctrl)

instructions.

–

The time base facility (TB) consists of two 32-bit registers, time base upper (TBU)

and time base lower (TBL). User-level software can read (but not write) to these

two registers.

–

SPRG4–SPRG7. Software-use special-purpose registers (SPRGs). SPRG4–

SPRG7 are read only by user-level software. The e200z3 does not allow user-

mode access to SPRG3. Book E defines such access as implementation-

dependent.

–

USPRG0. User-software-use SPR USPRG0, which is read-write accessible to

user-level software.

Supervisor-level registers, which are control and status registers accessible to supervisor-

level software. An operating system might use these registers for configuration, exception

handling, and other operating system functions:

●

Processor control registers

–

Machine state register (MSR). Defines the state of the processor. The MSR can be

modified by the move to machine state register (mtmsr), system call (sc), and

return from interrupt (rfi, rfci, rfdi) instructions. It can be read by the move from

machine state register (mfmsr) instruction. When an interrupt occurs, the contents

of the MSR are saved to one of the machine state save/restore registers (SRR1,

CSRR1, DSRR1).

–

Processor version register (PVR). A read-only register that identifies the version

(model) and revision level of the PowerPC processor.

–

Processor identification register (PIR). A read-only register to distinguish the

processor from other processors in the system.

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Storage control registers

–

Process ID register (PID0, also referred to as PID). Indicates the current process

or task identifier. The MMU uses it as an extension to the effective address, and

the external Nexus 2 module uses it for ownership trace message generation.

PowerPC Book E allows multiple PIDs; the e200z3 implements only one.

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Interrupt registers

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