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AN4253 数据表(PDF) 9 Page - STMicroelectronics |
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AN4253 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 44 page  DocID024255 Rev 2 9/44 AN4253 After reset init Figure 3. MMU reset configuration 2.2.1 Default reset configuration • 4 KB code Flash area starting at reset vector 2.2.2 Code sequence Memory management unit is a part of the core with its dedicated register interface (MASx) to access an internal MMU configuration. Read operation sequence 1. Prepare MMU item number in MAS0 register (mtspr instruction) 2. Execute tlbre instruction 3. Content of table entry is read to MAS0-3 register (mfspr instruction) Write operation sequence 1. Prepare configuration in MAS0-3 registers (mtspr instruction) 2. Execute tlbwe instruction 3. Content of MAS0-3 registers is written to MMU entry |
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