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AN4253

HW resource initialization

circumstances different values in both cores can lead to the reset because of RCCU

(checker blocks) event.

In decoupled mode, it is not necessary to have this explicit initialization.

7.3.1

Code sequence

No need to initialize core registers.

7.4

Cache memory initialization

Cache memory initialization does not bring any advantage for a simple startup code with a

sequential flow and small loops that fit into buffer lines of PFlash controller. Default PFlash

setup can store up to twelve 32 bit instruction or twenty-four 16 bit instructions.

Of course cache memory should be enabled somewhere in the startup code, because it

brings significant increase in performance (~30 %). If the startup code is the place of

initialization, cache enable bit in L1CSR1 special function register must be set.

7.4.1

Default reset configuration

•

Cache disabled

7.4.2

Code sequence

Enable cache (bit ICE) in Core L1CSR1 special function register

7.5

Branch prediction

Z4 core implemented on the SPC564Lx device contains simple branch target buffer

prediction feature that brings small performance increase for an application code.

It is not really needed to be done in the startup code, but if the startup is the place of

initialization, code shall enable the branch prediction in BUCSR special purpose register.

7.5.1

Default reset configuration

•

Branch target buffer prediction disabled

7.5.2

Code sequence

Set BPEN bit in BUCSR core register

7.6

Clock system initialization

Clock subsystem consists of clock generators, clock selectors with dividers and clock

monitor units.

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