AN4253 datasheet(39/44 Pages) STMICROELECTRONICS

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AN4253

asm examples

se_b .

// here infinitive loop

me_end:

A.8

AIPS protection

aips_start:

e_lis

r7, AIPS_BASE@h

e_or2i

r7, AIPS_BASE@l

// r7 = AIPS bridge base address

e_lis

r0, AIPS_MPROT_ENABLE@h

e_or2i

r0, AIPS_MPROT_ENABLE@l

// value to write to AIPS MPROT register

se_stw

r0, AIPS_REG_MPROT (r7)

// write the value

A.9

Cache memory initialization

init_cache:

e_li

r0, CACHE_ICE_BIT

// prepare ICE bit to enable the cache

mtspr

CACHE_REG_L1CSR1, r0 // enable Cache

A.10

Branch prediction

mfbucsr

// read BUCSR special function register

e_or2i

r3, 0x1

// set branch prediction bit

mtbucsr

// write value back to enable it

A.11

Clock system initialization

// setup CGM and ME base addresses

e_lis

r6, CGM_BASE@h

e_or2i

r6, CGM_BASE@l

e_lis

r7, ME_BASE@h

e_or2i

r7, ME_BASE@l

// setup EOCV value in XOSC block

e_lhz

r0, XOSC_REG_OSCCTL (r6) // get half word with EOCV bit field

e_and2i. r0, XOSC_EOCV_IMASK

// clear EOCV field

e_or2i

r0, XOSC_EOCV_VALUE

// set new value

e_sth

r0, XOSC_REG_OSCCTL (r6) // write it back

// enable XOSC in DRUN mode

e_lwz

r0, ME_REG_DRUN_MC (r7)

// read ME_DRUN_MC register

se_bseti r0, ME_MC_XOSCON

// set on XOSCON bit

e_stw

r0, ME_REG_DRUN_MC (r7)

// write value back

// mode transition -> DRUN

e_lis

r0, ME_MCTL_DRUN_R1@h

e_or2i

r0, ME_MCTL_DRUN_R1@l

e_stw

r0, ME_REG_MCTL (r7)

// 1. step - normal key

e_lis

r0, ME_MCTL_DRUN_R2@h

e_or2i

r0, ME_MCTL_DRUN_R2@l

AN4253 数据表(PDF) 39 Page - STMicroelectronics

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AN4253 数据表(PDF) 39 Page - STMicroelectronics

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