TN0108

Peripherals

Doc ID 15874 Rev 2

13/26

5.4

ADC multiplex control

On Cut 1 devices, the ADC multiplexer pins, MA[0..2], are brought out in two possible

positions, as detailed in the table below.

On Cut 2 devices, an additional pad multiplexing for MA[0] and MA[1] has been added.

5.5

ADC clock prescaler divider

On Cut 1.1 devices, the ADC clock prescaler has a fixed divide ratio of system clock/2. This

gives a minimum conversion time of 2µS when running from the 16 MHz IRC. If the device is

in the dynamic stage of a low-power sequence, this will extend the time that the user has to

stay operational, rather than in a LP mode, so increasing the average power consumption.

To address this problem on Cut 2 devices, an ADCCLKSEL (ADC Clock Frequency Select)

bit was added to the ADC_MCR (Main Configuration Register). This bit can be written to set

the ADC clock to the system frequency.

Table 10.

MA[0..2] pad multiplexing locations

Register bits

Description

Alternate function

SPC560B Cut 1.1

SPC560B Cut 2

MA[0]

PE7

AF3

•

-

PH8

AF3

•

•

PC3

AF2

-

•

MA[1]

PE6

AF3

•

•

PH7

AF3

•

•

PC10

AF3

-

•

MA[2]

PE5

AF3

•

•

PH6

AF3

•

•

Table 11.

ADC clock prescaler

Silicon revision

ADC clock prescaler

ADC clock

SPC560B Cut 1.1

Hard wired

sys_clk/2

SPC560B Cut 2

ADCCLKSEL = 0

sys_clk/2

1.

The configuration of ADC clock = system clock is only valid for LPM wakeup when running on the 16 MHz

IRC. The ADCCLKSEL bit can ONLY be written in ADC power down mode. In all other cases, the ADC

clock should be set to system clock/2.

sys_clk