TN0108

Summary of differences

Doc ID 15874 Rev 2

5/26

1

Summary of differences

This section gives a summary of all the differences between the SPC560B 512 KB Flash

size silicon revisions Cut 1.1 and Cut 2. These differences are described in more detail in

the following sections. For ease of navigation, the section number provides a link to the

appropriate section.

Table 2.

Summary of differences

Description

Cut 1.1

Cut 2

Section

SRAM size increase

32 KB SRAM

48 KB SRAM

Section 2.1

Additional GPIO on JTAG pins

Dedicated JTAG pins

Added PH[9] and PH[10] to

TMS and TCK

Section 3.1

Medium speed pad allocation

27 additional medium pads

Section 3.2

GPIO state during and after reset

High-Z in reset, then input

with weak pull-up

High-Z during and after reset

except JTAG and ABS pins

Section 3.3

Debug through LPM

Not supported

Supported

Section 4.1

JTAG operation in safe mode

JTAG pins tri-state by default

in SAFE mode

SMC modified, so JTAG pins

remain active in SAFE mode

Section 4.2

Nexus TAP change

Change to TAP command

Section 4.3

Peripheral clock prescalers

Disabled out of reset

Enabled out of reset

Section 5.1

ADC register map change

Fundamentally different to

Cut 2. Code change required.

Section 5.2

ADC additional external result

register

Four external results

registers for ANX[0..3]

32 external results registers

covering full external mux

Section 5.3

ADC multiplex control

Additional pad-multiplexing

options.

Section 5.4

ADC clock prescaler divider

Set to sysclk/2

Option to use sysclk/2 when in

LPM on 16 MHz IRC

Section 5.5

ADC abort

Slow abort for chained

commands

New “abortchain” control bit

added for rapid abort.

Section 5.6

ADC offset calculation

Implemented

Removed. Did not provide any

benefit to ADC precision.

Section 5.7

LINFlex configuration change

All four LINFlex modules

support master/slave

LINFlex 0 is master /slave, all

others are master only

Section 5.8

LINFlex slave filters

Eight ID filters on LINFlex0

16 ID filters on LINFlex0

Section 5.9

eMIOS additional modes and

channel types

Eight modes and three

channel types

Added two more channel

types with four more modes

Section 5.10

RCHW format

0x0000_005A

0x005A_0000

Section 6.1

Correct reset event disable

Can disable all reset sources

in DERD/FERD

Allow ability to lock all reset

config registers

Section 6.2

Protection of reset event disable

registers

Write-once protection based

on 32-bit resolution

Individual 16-bit protection for

DERD/FERD

Section 6.3