TN0108

Power, low power, and wakeup

Doc ID 15874 Rev 2

23/26

9

Power, low power, and wakeup

9.1

API/RTC wakeup source

On Cut 1 devices, the RTC and API shared the same wakeup source.

On Cut 2 devices, the API is wakeup source zero and the RTC is wakeup source one.

9.2

Halt mode defect fixed

Cut 1 devices have a problem entering Halt mode due to synchronization problem. This has

been fixed on Cut 2 devices.

9.3

Standby mode exit Flash control

The DFlash and CFlash can be independently controlled to be enabled on exit from standby

mode (entry into DRUN mode). The mechanism for this is different between Cut 1.1 and

Cut 2 devices.

On Cut 1.1, the DFlash and CFlash enable out of standby are controlled via the

DRUN_DFLA and DRUN_CFLA bits in the RGM_STDY register.

On Cut 2, the DFlash and CFlash DRUN entry state after Standby mode are controlled via

the DFLAON and CFLAON bits in the ME_DRUN_MC register.

9.4

Voltage regulator power up current clamping

On Cut 1.1 devices, there is a potential issue when exiting standby mode, whereby the

voltage regulator can draw a large current spike. This current draw was not regulated and

required sizeable bulk storage capacitors on the customer board to prevent the voltage

dipping with potential reset consequences.

Table 24.

Wakeup sources

Silicon revision

Source zero

Source one

SPC560B Cut 1.1

Shared API/RTC

1.

Note that the Cut 1.1 wakeup source one, PA0, has been replaced by the RTC on Cut 2 devices. PA0

wakeup has been moved to the end of the wakeup table. All other wakeup sources remain the same

between revisions. If you were using the API, RTC, or PA0 wakeup sources, then you need to ensure that

Cut 2 device code takes account of these changes. Consult the device reference manual for the full

wakeup source list.

SPC560B Cut 2

API

RTC

Table 25.

Standby mode exit Flash control

Silicon revision

Enable DFLASH

Enable CFLASH

SPC560B Cut 1.1

DRUN_DFLA bit in RGM_STDY

register

DRUN_CFLA bit in RGM_STDY

register

SPC560B Cut 2

DFLAON bit in ME_DRUN_MC

register

CFLAON bit in ME_DRUN_MC

register