AN1506 - APPLICATION NOTE

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The strip-based layout is a new approach [2], which allows using a simplified process for implanting the

body and isolating the poly silicon gate from the source. The new technology is very effective in

eliminating the limit of the cell-based layout, which relies on the capability to open smaller and smaller

windows on the poly silicon area in order to obtain greater cell-density figures. With the strip-based

layout, MOSFET devices show improved performances and a simpler manufacturing process. Moreover,

they benefit of the well-established and advanced design rules typical of VLSI processes. On-state

resistance values as low as 1.2m

Ω can be reached, but the overall MOSFET design must account for the

best trade-off of a merit figure, which is the product of the on-state resistance and the gate charge values

In this paper the main issues of the new technology are briefly recalled, and the device structure is

described and discussed. The static and dynamic characteristics of devices belonging to this new family

of MOSFETs are presented and compared with those of more traditional ones. Conventional

experimental tests have been carried out and are discussed aiming to determine the impact of turn on

and turn off energy loss [3]. A low-voltage battery-powered converter for wheel chairs is used as a

workbench for an application-oriented characterization. Some relevant tests are reported and discussed.

A detailed analysis is done on the conduction and switching losses and the thermal behavior in the actual

application.

3. MAIN TECHNOLOGY ISSUES OF STRIP-BASED MOSFET.

The structure of a strip-based MOSFET device overcomes the limit of a cell structure. In figure 1 the

geometry of the two differently conceived devices are shown. The main differences between a standard

square-cell layout and the strip implementation may be better understood by inspecting figure 2. In the

conventional cell structure shown, all subsequent contacts and isolation openings must be confined and

aligned inside the largest square windows opened on the poly silicon layer whose side is L in figure 2.

That dimension depends on the alignment, the resolution, and the process tolerances and can be

expressed as:

where:

• c is the contact dimension for the body region imposed by the resolution of the photolithography

equipment;

• b is the contact dimension for the source region which depends on the alignment capability and on the

metallization process;

• t is the separation (isolation) between the poly and source metal and is controlled by the alignment

feature.

Consequently, the standard cell layout depends on three feature sizes.

Lc

2b

2t

++

=1

()