AN413 datasheet(6/45 Pages) STMICROELECTRONICS

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ST9 basic system configuration

AN413

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Doc ID 1875 Rev 2

ST9 basic system configuration

Table 3 and Table 3 in Appendix A list the registers which should be loaded with specified

bit-patterns in order to initialize the ST9 to a basic system configuration. A demonstration

routine which carries this out for a representative ST9 system is listed in Appendix B. The

main routine, RESET_START, is invoked at system Reset. Also shown in Appendix B are

the Assembler Declarations and directives which enable the Interrupt Vector Address Table

to be set up in program memory.

3.1

The vector address table

The ST9 implements an interrupt vectoring structure that allows the on-chip peripheral to

identify the location of the first instruction of the Interrupt Service Routine (ISR). Each

interrupt module has a specific Interrupt Vector Register (IVR) mapped on the register file

pages. When the interrupt request is acknowledged, the peripheral interrupt module

provides, via the IVR, the vector to point to the address of the Interrupt Service Routine in

the Vector Table.

The Interrupt Vector table containing the list of addresses of the Interrupt Service Routine

must be located in the first 256 locations of program memory. The first 6 locations of

Program memory are reserved as follows:

Note that since the above locations are fixed by the hardware no associated IVR register is

involved. For certain interrupt modules more than one interrupt routine may be required. For

example the A/D Converter has separate interrupts for the End of Conversion and Channel

6/7 analog underflow/overflow conditions.

In such cases the IVR register specifies the more significant, and the interrupt module

hardware specifies the least significant bits of the Vector Table address.

The following Assembler outline shows how the corresponding Vector table entries may be

established.

ADC_IT_VECT:= 30h

.org ADC_IT_VECT

.word ADC_WDG

Table 1.

Reserved locations of program memory

Address

Content

Address high of Power on Reset routine

Address low of Power on Reset routine

Address high of Divide by Zero Trap Subroutine

Address low of Divide by Zero Trap Subroutine

Address high of Top Level ISR

Address low of Top Level ISR

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