AN413 datasheet(4/45 Pages) STMICROELECTRONICS

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System reset

AN413

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Doc ID 1875 Rev 2

System reset

After processor Reset the control and status registers, located on the group F pages (0-63)

are forced to preset values which define a default Reset configuration for the ST9 system.

By way of example the internal clock frequency (INTCLK) is set to the internal crystal

oscillator (or externally applied clock frequency, if supplied) divided by two without

prescaling, and the individual pins of Parallel Ports 0,1, and 6 are set to bidirectional Pull-up

mode (for systems with on-chip ROM). On releasing the external RESET signal the

processor PC is loaded with the contents of the Reset Vector stored in address locations 0

and 1. This causes a jump to a Reset routine in which the designer may reconfigure the ST9

system as appropriate to the requirements of his particular application, by loading suitable

values into the system registers.

The number of registers to be initialized may be considerable for a representative ST9

system. Additionally, the application-specific interrupt routines will, in general, involve the

manipulation of substantial system resources, e.g. read/write of data registers, and

test/reset of status, mask, and control registers. The associated programming task may

appear daunting in prospect on first acquaintance with the ST9 system.

Conceptually, the organization of the associated software is relatively simple and

straightforward as may be recognized by grouping under four headings the programming

steps involved in the initialization of ST9 peripherals and the organization of interrupt service

routines.

a) ST9 core system configuration

Certain core system resources are common to all on-chip peripherals and may be

specified in a common routine which is invoked at System Reset. Such common

resources include clock configuration, system and user stack specification, global

interrupt masking, processor priority setting, parallel port bit-by-bit specification, and

setting of external memory wait-cycles. The setting up of the interrupt vector table, and

certain global masking or enabling operations, may also be included under this

heading.

b) Individual on-chip peripheral configuration

The configuration of on-chip peripherals, e.g. Multifunction Timers, A/D Converters,

etc., involves the loading of suitable bit-patterns into group F page registers. This

enables the specification of input and output signals, determination of the peripheral’s

mode of operation, and the selection of internal or external clock and control signals.

c) Individual on-chip peripheral initialization

The initialization of a particular on-chip peripheral may involve the setting or clearing of

device-specific enable and masking bits, specification of interrupt priority levels,

clearing of status/flag values, and the loading of data and/or limit registers.

d) Organization of interrupt service routines

This will normally include context-saving and restoring of the PC and system status,

plus the working-register and page-pointer registers, together with the values of any

working registers used in the routine. The routine proper may include testing of status

flag bits, and the reading and writing of data registers associated with the particular

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