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ST7 AND ST9 PERFORMANCE BENCHMARKING

7.3.2 68HC16 MCU core

Memory Spaces

Harvard organization

- pseudo-linear data/program memory space

data memory space

16 banks of 64 kbytes each = 1 Mbyte

peripheral registers in last segment

program memory space

16 banks of 64 kbytes each = 1 Mbyte

first 512-byte interrupt vector table = 207 interrupts

On-chip/Off-chip buses

- on-chip buses

16-bit address bus + 4-bit extension (= 20 bits)

extensible up to 24 bits

8/16-bit multiplexed data/program memory bus

- off-chip buses

16-bit address bus + 4-bit extension (= 20 bits)

extensible up to 24 bits

8/16-bit multiplexed data/program memory bus

the two buses are multiplexed with ports

Arithmetic Logic Unit

16-bit datapath

- 8/16/32-bit operations

- special functions

8x8 unsigned multiplication

10 cycles

16x16 (un)signed multiplications

(8)10 cycles

16x16 fractional signed multiplication8 cycles

32/16 (un)signed divisions

(24)38 cycles

16/16 fractional unsigned division

22 cycles

16/16 integer division

22 cycles

mac signed 16-bit fractions

12 cycles

r(epeat) mac signed 16-bit fractions 6+12n cycles

Instruction processing

Prefetch mechanism

- 3-stage queue

stage A : latched opcode

stage B : executing opcode

stage C : hold opcode

- predecoding

- word operand even/odd alignment

substantial performance penalty if odd alignment

Cpu internal buses

16-bit address bus, 16-bit data bus

(to be confirmed)

Instruction set

Cisc encoding

- CPI

2 cycles to 38 cycles

- average CPI

between 6 and 7 cycles

- IL

2 bytes to 6 bytes (even)

- average IL

between 3 and 4 bytes

- special addressing modes

accumulator offset

indexed with 8/16/20-bit offset

post-modified indexed mode with 8-bit offset

- special instructions

32-bit long integer manipulations

exchange register contents

push/pull multiple registers

memory-to-memory moves

extended

↔ post-modified indexed

extended

↔ extended

mac and r(epeat)mac instructions

LDAA

#8, X

ADDA #A0

+ / x

Programming model

Accumulators

- two 16-bit accumulators

useable as one 32-bit accumulator

first addressable as two 8-bit registers

- three 16-bit index registers

with 4-bit extension

- others registers

16-bit program counter (with 4-bit extension)

16-bit stack pointer (with 4-bit extension)

condition code register

two 16-bit & one 36-bit & one 16-bit mac registers

operand registers, result register, mask register

- extension fields

four 4-bit index address extension fields

one 4-bit stack address extension fields

- multitasking capabilities

context switching with extension fields

68HC16 CPU

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