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UPD6708 数据表(PDF) 65 Page - NEC |
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UPD6708 数据表(HTML) 65 Page - NEC |
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65 / 72 page ![]() 65 µPD6708 PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT System clock fX = 12 MHz Using communication mode 2 11.94 12.00 12.06 MHz Using communication mode 0,1 11.82 12.00 12.18 MHz fX = 12.58 MHz Using communication mode 2 12.52 12.58 12.64 MHz Using communication mode 0,1 12.40 12.58 12.76 MHz SCK cycle time tKCY 0.8 µs SCK high-level width tKH 0.4 µs SCK low-level width tKL 0.4 µs SI setup time (to SCK ↑)tSIK 100 ns SI hold time (from SCK ↑)tKSI 400 ns SO output delay time (from SCK ↑) tKSO 300 ns CS, C/D, R/W setup time (to SCK ↑) tSA 0ns CS, C/D, R/W hold time (from SCK ↑) tHA 400 ns CS high-level width 400 ns IRQ output high-level width 8 11 µs RESET low-level width 6 µs Oscillation stabilization time tOS fX = 12 MHz 20 ms AC Characteristics (TA = –40 to +85 °C, VDD = AVDD = 5 V ±10 %) Serial Transfer Timing CS, C/D, R/W SCK SI SO tSA tHA tKYC tKL tKH tSIK tKSI Data Input Data Output tKSO |
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