UPD6708 datasheet(22/72 Pages) NEC

22 / 72 page

µPD6708

INTERFACING WITH HOST CONTROLLER

This chapter will explain the interfacing that occurs between the

µPD6708 and the host controller.

4.1

Accessible Buffers and Registers from Host Controller

The host controller, which controls the

µPD6708, can access the write data (WDB), the read data buffer (RDB), the

command register (CMR), and the status register (STR) within the

µPD6708.

4.1.1

Write data buffer (WDB)

WDB is a 4-byte FIFO buffer in which the host controller transmit data and the parameters of the communication control

commands are written.

4.1.2

Read data buffer (RDB)

RDB is a 20-byte FIFO buffer which stores the receive data acknowledged by the data link layer controller in the

µPD6708.

The host controller reads the

µPD6708 receive data from RDB.

4.1.3

Command register (CMR)

CMR is an 8-bit register used to write control commands for the

µPD6708.

As shown in Table 4-1, the host controller sets the reset mode and the host interface mode in higher 4 bits and sets the

communication control command code in lower 4 bits.

Table 4-1. Contents of Command Register

Bit

Value

Meaning

Bit 7

Entering the reset mode

Exiting the reset mode

Bit 6

Data of lower 4 bits of CMR is valid.

Data of lower 4 bits of CMR is not valid.

Bit 5

Change of mode through pin control

Switches the host interface mode

Bit 4

Data write mode

Data read mode

Status read mode

Bit 3 to

Set the communication control command codes

Bit 0

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