PM0068

Overview

Doc ID 17100 Rev 2

7/31

For write and erase operations on the Flash memory (write/erase), the internal RC oscillator

(HSI) must be ON.

The Flash memory can be programmed and erased using in-circuit programming and in-

application programming.

Note:

In the low-power modes, all Flash memory accesses are aborted. Refer to the

STM32F10xFG reference manual for further information.

1.3

Dual bank architecture

The XL-density Flash memory features a dual bank architecture based on bank 1

(512 Kbytes) and bank 2 (up to 512 Kbytes). This architecture supports the RWW (read-

while-write) capability. This means that while a read or program operation is performed in a

bank, the other bank can be accessed for another operation (read or program) without the

need to wait for the End of Operation on the first bank.

The registers that control the Flash memory are divided into two categories:

●

Registers for Flash memory access control (FLASH_ACR) and option bytes

management (FLASH_OPTKEYR, FLASH_OBR and FLASH_WRPR). These registers

are common to both banks. Option bytes programming is controlled through

FLASH_CR register.

●

A dedicated set of registers allows to control and program each bank; FLAH_KEYRx,

FLASH_SRx, FLASH_CRx and FLASH_ARx. However, the programming procedure is

identical for both banks. As an example, to perform a page erase on bank 1, the user

code must write to FLASH_CR register, while it must write to FLASH_CR2 for bank 2.

In the rest of the document:

●

Section 2.2 to Section 2.3.4 apply to both banks. However for simplification purposes,

only one bank will be referred to. The user code must use the registers corresponding

to the selected bank.

●

Section 2.3.5 and Section 2.4 describe option bytes management and are

consequently common to both banks. The user code must program the same set of

registers whatever the bank.