PM0068

Register descriptions

Doc ID 17100 Rev 2

21/31

3.2

FPEC key register (FLASH_KEYR)

This register is dedicated to Flash memory bank 1.

Address offset: 0x04

Reset value: xxxx xxxx

Note:

These bits are all write-only and will return a 0 when read.

3.3

Flash OPTKEY register (FLASH_OPTKEYR)

Address offset: 0x08

Reset value: xxxxx xxxx

Note:

These bits are all write-only and will return a 0 when read.

Bits 2:0 LATENCY: Latency

These bits represent the ratio of the SYSCLK (system clock) period to the Flash access

time.

000 Zero wait state, if 0 < SYSCLK

≤ 24 MHz

001 One wait state, if 24 MHz < SYSCLK

≤ 48 MHz

010 Two wait states, if 48 MHz < SYSCLK

≤ 72 MHz

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16

FKEYR[31:16]

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0

FKEYR[15:0]

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Bits 31:0 FKEYR: FPEC key

These bits represent the keys to unlock the FPEC.

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OPTKEYR[31:16]

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OPTKEYR[15:0]

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Bits 31:0

OPTKEYR: Option byte key

These bits represent the keys to unlock the OPTWRE.