PM0075

Reading/programming the embedded Flash memory

Doc ID 17863 Rev 2

13/31

2.3.2

Unlocking the Flash memory

After reset, the FPEC block is protected. The FLASH_CR register is not accessible in write

mode. An unlocking sequence should be written to the FLASH_KEYR register to open up

the FPEC block. This sequence consists of two write cycles, where two key values (KEY1

and KEY2) are written to the FLASH_KEYR address (refer to Section 2.3.1 for key values).

Any wrong sequence locks up the FPEC block and FLASH_CR register until the next reset.

Also a bus error is returned on a wrong key sequence. This is done after the first write cycle

if KEY1 does not match, or during the second write cycle if KEY1 has been correctly written

but KEY2 does not match. The FPEC block and FLASH_CR register can be locked by the

user’s software by writing the LOCK bit of the FLASH_CR register to 1. In this case, the

FPEC can be unlocked by writing the correct sequence of keys into FLASH_KEYR.

2.3.3

Main Flash memory programming

The main Flash memory can be programmed 16 bits at a time. The program operation is

started when the CPU writes a half-word into a main Flash memory address with the PG bit

of the FLASH_CR register set. Any attempt to write data that are not half-word long will

result in a bus error response from the FPEC. If a read/write operation is initiated during

programming, (BSY bit set), the CPU stalls until the ongoing main Flash memory

programming is over.

Figure 1.

Programming procedure

Read FLASH_CR_LOCK

FLASH_CR_LOCK

= 1

Yes

No

Yes

No

Perform unlock sequency

Write FLASH_CR_PG to 1

Perform half-word write at the

desired address

FLASH_SR_BSY

= 1

Check the programmed value

by reading the programmed

address

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