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Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

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Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

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Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

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High-density devices are STM32F101xx and STM32F103xx microcontrollers where

the Flash memory density ranges between 256 and 512 Kbytes.

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Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

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The Cortex-M3 core integrates two debug ports:

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JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the

Joint Test Action Group (JTAG) protocol.

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SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on

the Serial Wire Debug (SWD) protocol.

For both the JTAG and SWD protocols please refer to the Cortex M3 Technical

Reference Manual

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Word: data/instruction of 32-bit length

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Half word: data/instruction of 16-bit length

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Byte: data of 8-bit length

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FPEC (Flash memory program/erase controller): write operations to the main memory

and the information block are managed by an embedded Flash program/erase

controller (FPEC).

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IAP (in-application programming): IAP is the ability to re-program the Flash memory of

a microcontroller while the user program is running.

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ICP (in-circuit programming): ICP is the ability to program the Flash memory of a

microcontroller using the JTAG protocol, the SWD protocol or the boot loader while the

device is mounted on the user application board.

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I-Code: this bus connects the Instruction bus of the Cortex-M3 core to the Flash

instruction interface. Prefetch is performed on this bus.

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D-Code: this bus connects the D-Code bus (literal load and debug access) of the

Cortex-M3 to the Flash Data Interface.

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Option bytes: product configuration bits stored in the Flash memory

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OBL: option byte loader.

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AHB: advanced high-performance bus.