PM0075

Register descriptions

Doc ID 17863 Rev 2

23/31

3

Register descriptions

In this section, the following abbreviations are used:

Note:

The Flash memory registers have to be accessed by 32-bit words (half-word and byte

accesses are not allowed).

3.1

Flash access control register (FLASH_ACR)

Address offset: 0x00

Reset value: 0x0000 0030

Table 10.

Abbreviations

Abbreviation

Meaning

read/write (rw)

Software can read from and write to these bits.

read-only (r)

Software can only read these bits.

write-only (w)

Software can only write to this bit. Reading the bit returns the reset

value.

read/clear (rc_w0)

Software can read as well as clear this bit by writing ‘0’. Writing ‘1’ has

no effect on the bit value.

read/set (rs)

Software can read as well as set this bit. Writing ‘0’ has no effect on

the bit value.

Reserved (Res.)

Reserved bit, must be kept at reset value.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

PRFT

BS

PRFT

BE

HLF

CYA

LATENCY

rrw

rw

rw

rw

rw

Bits 31:6 Reserved, must be kept cleared.

Bit 5 PRFTBS: Prefetch buffer status

This bit provides the status of the prefetch buffer.

0: Prefetch buffer is disabled

1: Prefetch buffer is enabled

Bit 4 PRFTBE: Prefetch buffer enable

0: Prefetch is disabled

1: Prefetch is enabled

Bit 3 HLFCYA: Flash half cycle access enable

0: Half cycle is disabled

1: Half cycle is enabled