8

LTC1402

GAIN (Pin 7): Tie to AGND2 to set the reference voltage to

(Note 4)

BIP/UNI (Pin 8): Tie to logic low to set the input range to

unipolar mode or tie to logic high to set the input range to

bipolar mode. (Note 4)

OGND (Pin 9): Output Ground for the Output Driver. This

pin can be tied to the digital ground of the system. All other

ground pins should be tied to the analog ground plane.

output data word represents the analog input at the start

of the previous conversion.

driving 5V logic. Tie to 3V when driving 3V logic.

DGND with 10

µF ceramic (or 10µF tantalum in parallel

with 0.1

µF ceramic).

DGND (Pin 13): Digital Ground for Internal Logic. Tie to

solid analog ground plane.

analog ground plane with 10

µF ceramic (or 10µF tantalum

in parallel with 0.1

µF ceramic) or tie directly to the solid

analog ground plane for single supply use. Must be set

SCK (Pin 15): External Clock. Advances the conversion

rising edge. Responds to 5V or 3V CMOS and to TTL levels.

(Note 4). One or more pulses wake from Nap or Sleep.

CONV (Pin 16): Holds the input analog signal and starts

the conversion on the rising edge. Responds to 5V or 3V

CMOS and to TTL levels. (Note 4). Two pulses with SCK in

fixed high or fixed low state start Nap Mode. Four pulses

with SCK in fixed high or fixed low state start Sleep mode.

BLOCK DIAGRA

12-BIT CAPACITIVE DAC

COMP

REF AMP

+

–

2.048V REF

64k

GAIN

CONTROL LOGIC

SCK

CONV

16

15

INTERNAL

CLOCK

OUTPUT

DRIVER

ZEROING SWITCHES

1

12

14

8

10

11

9

BIP/UNI

OGND

+

3

4

7

5

6

2

13

–

AGND1

AGND2

DGND

1402 BD

+

–

SUCCESSIVE APPROXIMATION

REGISTER

64k