16

LTC1402

edge of CONV. Please note the delay specification from

by the next rising edge of SCK.

DIGITAL JITTER AT CONV (PIN 16)

In high speed applications, where high amplitude sinewaves

above 100kHz are sampled, the CONV signal must have as

little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

this requirement easily. The challenge is to generate a CONV

signal from this crystal clock without jitter corruption from

other digital circuits in the system. A clock divider and any

gates in the signal path from the crystal clock to the CONV

input should not share the same integrated circuit with

other parts of the system. As shown in the interface circuit

examples, the LTC1402’s SCK and CONV inputs should be

driven first with digital buffers used to drive the serial port

interface. Also note that the master clock in the DSP may

already be corrupted with jitter, even if it comes directly

from the DSP crystal. Another problem with high speed

processor clocks is that they often use a low cost, low

speed crystal (i.e., 10MHz) to generated a fast, but jittery,

phase locked loop system clock (i.e., 40MHz). The jitter, in

these PLL-generated high speed clocks, can be several

nanoseconds. Note that if you choose to use the frame

sync signal generated by the DSP port, this signal will have

the same jitter of the DSP’s master clock.

SERIAL TO PARALLEL CONVERSION

You can take advantage of the serial interface of the LTC1402

in a parallel data system to minimize bus wiring conges-

tion in the PC board layout. Figure 12 shows an example

of this interface. It is best to send the SCK and CONV

signals to the LTC1402, and then bus them together across

the board to avoid excessive time skew among the three

track is not too long. Buffering SCK and CONV prevents

jitter from corrupting these signals. The relative phase

between SCK and CONV affects the position of the parallel

word at the output of the 74HC595. The position of the

output word in Figure 12 assumes 16 clocks between each

CONV rising edge, and the CONV pulse is one clock wide.

Figure 12. Serial to Parallel Interface

SRCLR

QA

QB

QC

QD

QE

QF

QG

RCK

SRCK

SER

G

QH

QH

′

15

1

2

3

4

5

6

12

10

10

11

14

13

7

9

SRCLR

QA

QB

QC

QD

QE

QF

QG

RCK

74ACT04

SRCK

SER

74HC595

74HC595

G

11

5V

16

15

10

9

3-WIRE SERIAL

INTERFACE LINK

QH

QH

′

15

1

2

3

4

5

6

12

11

14

13

1402 F12

7

D0

D1

D2

D3

D4

D5

D7

D8

D9

D10

D11

REFRDY

D6

9

CONV

SCK

LTC1402

OGND

CONV

CLK