17

LTC1402

Figure 13. DSP Serial Interface to TMS320C54x

1402 F13

11

16

15

10

9

3-WIRE SERIAL

INTERFACE LINK

CONV

SCK

LTC1402

BFSR

BCLKR

TMS320C54x

BDR

OGND

CONV

CLK

5V

REF

B11

B10

HARDWARE INTERFACE TO TMS320C54x

The LTC1402 is a serial output ADC whose interface has

been designed for high speed buffered serial ports in fast

digital signal processors (DSPs). Figure 13 shows an

example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial data

can be collected in two alternating 1kB segments, in real

time, at the full 2.2Msps conversion rate of the LTC1402.

The DSP assembly code sets frame sync mode at the BFSR

pin to accept an external positive going pulse, and the

serial clock at the BCLKR pin to accept an external positive

edge clock. Buffers near the LTC1402 may be added to

drive long tracks to the DSP to prevent corruption of the

signal to LTC1402. This configuration is adequate to

traverse a typical system board, but source resistors at the

buffer outputs, and termination resistors at the DSP may

be needed to match the characteristic impedance of very

transmission line, buffer it first with one or two 74ACxx

gates. The TTL threshold inputs of the DSP port respond

properly to the 2.5V swing of the terminated transmission

driven directly from the DSP.

; ***************************************************************************

; Files: BSP2KB.ASM ->

; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402

; first element at 1024, last element at 1023, two middle elements at 2047 and 0000

; bipolar mode

; ***************************************************************************

.width

160

.length

110

.title “sineb0 BSP in auto buffer mode”

.mmregs

.setsect “.text”,

0x500,0

;Set address of executable

.setsect “vectors”, 0x180,0

;Set address of incoming 1402 data

.setsect “buffer”, 0x800,0

;Set address of BSP buffer for clearing

.setsect “result”,

0x1800,0

;Set address of result for clearing

.text

;.text marks start of code

start:

;Make sure /PWRDWN is low at J1-9 to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h

; stop timer

tspc = #0h

; stop TDM serial port to AC01

pmst = #01a0h ; set up iptr. Processor Mode STatus register

sp = #0700h

; init stack pointer.

dp = #0

; data page

ar2 = #1800h

; pointer to computed receive buffer.

ar3 = #0800h

; pointer to Buffered Serial Port receive buffer

ar4 = #0h

; reset record counter

call sineinit

; Double clutch the initialization to insure a proper

sinepeek:

; insert debugger break here to view results

call sineinit

; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait

goto wait