LTC1419ACSW datasheet(4/20 Pages) LINER

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LTC1419

Note 6: Linearity, offset and full-scale specifications apply for a single-

ended +AIN input with – AIN grounded.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB

when the output code flickers between 0000 0000 0000 00 and

1111 1111 1111 11.

Note 9: Guaranteed by design, not subject to test.

Note 10: Recommended operating conditions.

Note 11: The falling edge of CONVST starts a conversion. If CONVST

returns high at a critical point during the conversion it can create small

errors. For best performance ensure that CONVST returns high either

within 650ns after the start of the conversion or after BUSY rises.

(Note 5)

TI I G CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PDIS

Power Dissipation

150

240

Nap Mode

SHDN = 0V, CS = 0V

7.5

Sleep Mode

SHDN = 0V, CS = 5V

1.2

POWER REQUIRE E TS (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE(MAX)

Maximum Sampling Frequency

800

kHz

tCONV

Conversion Time

950

1150

tACQ

Acquisition Time

300

tACQ + CONV

Acquisition + Conversion Time

1040

1250

CS to RD Setup Time

(Notes 9, 10)

0ns

↓ to CONVST↓ Setup Time

(Notes 9, 10)

↓ to SHDN↓ Setup Time

(Notes 9, 10)

SHDN

↑ to CONVST↓ Wake-Up Time (Note 10)

400

CONVST Low Time

(Notes 10, 11)

CONVST to BUSY Delay

CL = 25pF

Data Ready Before BUSY

↑

Delay Between Conversions

(Note 10)

Wait Time RD

↓ After BUSY↑

–5

t10

Data Access Time After RD

↓

CL = 25pF

CL = 100pF

t11

Bus Relinquish Time

°C ≤ TA ≤ 70°C

–40

°C ≤ TA ≤ 85°C

t12

RD Low Time

t10

t13

CONVST High Time

The q denotes specifications which apply over the full operating

temperature range; all other limits and typicals TA = 25°C.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND and

AGND wired together unless otherwise noted.

Note 3: When these pin voltages are taken below VSS or above VDD, they

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below VSS, they will be clamped

by internal diodes. This product can handle input currents greater than

100mA below VSS without latchup. These pins are not clamped

to VDD.

Note 5: VDD = 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise

specified.

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