7

LTC1419

Load Circuits for Access Timing

Load Circuits for Output Float Delay

TEST CIRCUITS

1k

DBN

DBN

1k

5V

1419 TC01

1k

100pF

100pF

DBN

DBN

1k

5V

1419 TC02

CONVERSION DETAILS

The LTC1419 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 14-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs (please refer to Digital Interface section for

the data format).

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 14-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit (LSB).

ing the acquire phase and the comparator offset is nulled by

the zeroing switches. In this acquire phase, a minimum

delay of 200ns will provide enough time for the sample-

and-hold capacitors to acquire the analog signal. During

the convert phase the comparator zeroing switches open,

putting the comparator into compare mode. The input

the differential analog input charge onto the summing

junction. This input charge is successively compared with

the binary weighted charges supplied by the differential

capacitive DAC. Bit decisions are made by the high speed

comparator. At the end of a conversion, the differential

The SAR contents (a 14-bit data word) which represents

output latches.

DYNAMIC PERFORMANCE

The LTC1419 has excellent high speed sampling capabil-

ity. FFT (Fast Fourier Transform) test techniques are used

to test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion sine

wave and analyzing the digital output using an FFT algo-

rithm, the ADC’s spectral content can be examined for

Figure 1. Simplified Block Diagram

COMP

•

•

•

D13

D0

ZEROING SWITCHES

HOLD

HOLD

14

1419 F01

+

–

SAR

OUTPUT

LATCH

HOLD

HOLD

SAMPLE

SAMPLE