LTC2400CS8 datasheet(8/40 Pages) LINER

8 / 40 page

LTC2400

INL vs Output Rate

Resolution vs Output Rate

TYPICAL PERFOR A CE CHARACTERISTICS

VCC (Pin 1): Positive Supply Voltage. Bypass to GND

(Pin 4) with a 10

µF tantalum capacitor in parallel with

0.1

µF ceramic capacitor as close to the part as possible.

VREF (Pin 2): Reference Input. The reference voltage range

is 0.1V to VCC.

VIN (Pin 3): Analog Input. The input voltage range is

– 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V, the input

voltage range may be limited by the pin absolute maxi-

mum rating of – 0.3V to VCC + 0.3V.

GND (Pin 4): Ground. Shared pin for analog ground,

digital ground, reference ground and signal ground. Should

be connected directly to a ground plane through a mini-

mum length trace or it should be the single-point-ground

in a single point grounding system.

CS (Pin 5): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW on CS wakes up the ADC. A

LOW-to-HIGH transition on this pin disables the SDO

digital output. A LOW-to-HIGH transition on CS during the

Data Output transfer aborts the data transfer and starts a

new conversion.

OUTPUT RATE (Hz)

2400 G27

15 20 25

303540455055

VCC = 5V

VREF = 5V

TA = 25°C

F0 = EXTERNAL

OUTPUT RATE (Hz)

2400 G28

15 20 25

303540455055

VCC = 5V

VREF = 5V

TA = 25°C

FO = EXTERNAL

*RESOLUTION =

LOG(VREF/RMS NOISE)

LOG (2)

SDO (Pin 6): Three-State Digital Output. During the data

output period, this pin is used for serial data output. When

the chip select CS is HIGH (CS = VCC), the SDO pin is in a

high impedance state. During the Conversion and Sleep

periods this pin can be used as a conversion status output.

The conversion status can be observed by pulling CS LOW.

SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as digital output

for the internal serial interface clock during the data output

period. In External Serial Clock Operation mode, SCK is

used as digital input for the external serial interface. A

weak internal pull-up is automatically activated in Internal

Serial Clock Operation mode. The Serial Clock mode is

determined by the level applied to SCK at power up and the

falling edge of CS.

FO (Pin 8): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the FO pin is connected to VCC (FO = VCC), the

converter uses its internal oscillator and the digital filter

first null is located at 50Hz. When the FO pin is connected

to GND (FO = OV), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz. When FO

is driven by an external clock signal with a frequency fEOSC,

the converter uses this signal as its clock and the digital

filter first null is located at a frequency fEOSC/2560.

PIN FUNCTIONS

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