LTC2400CS8 datasheet(32/40 Pages) LINER

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LTC2400

TYPICAL APPLICATIONS

DIN1

EQU

$00

This memory location holds the LTC2400's bits 31 - 24

DIN2

EQU

$01

This memory location holds the LTC2400's bits 23 - 16

DIN3

EQU

$02

This memory location holds the LTC2400's bits 15 - 08

DIN4

EQU

$03

This memory location holds the LTC2400's bits 07 - 00

**********************

* Start GETDATA Routine *

**********************

ORG

$C000

Program start location

INIT1

LDS

#$CFFF

Top of C page RAM, beginning location of stack

LDAA

#$2F

–,–,1,0;1,1,1,1

–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X

STAA

PORTD

Keeps SS* a logic high when DDRD, bit 5 is set

LDAA

#$38

–,–,1,1;1,0,0,0

STAA

DDRD

SS*, SCK, MOSI are configured as Outputs

MISO, TxD, RxD are configured as Inputs

*DDRD's bit 5 is a 1 so that port D's SS* pin is a general output

LDAA

#$50

STAA

SPCR

The SPI is configured as Master, CPHA = 0, CPOL = 0

and the clock rate is E/2

(This assumes an E-Clock frequency of 4MHz. For higher E-

Clock frequencies, change the above value of $50 to a value

that ensures the SCK frequency is 2MHz or less.)

GETDATA PSHX

PSHY

PSHA

LDX

#$0

The X register is used as a pointer to the memory locations

that hold the conversion data

LDY

#$1000

BCLR

PORTD, Y %00100000

This sets the SS* output bit to a logic

low, selecting the LTC2400

TRFLP1

LDAA

#$0

Load accumulator A with a null byte for SPI transfer

STAA

SPDR

This writes the byte in the SPI data register and starts

the transfer

WAIT1

LDAA

SPSR

This loop waits for the SPI to complete a serial

transfer/exchange by reading the SPI Status Register

BPL

WAIT1

The SPIF (SPI transfer complete flag) bit is the SPSR's MSB

and is set to one at the end of an SPI transfer. The branch

will occur while SPIF is a zero.

LDAA

SPDR

Load accumulator A with the current byte of LTC2400 data

that was just received

STAA

0,X

Transfer the LTC2400's data to memory

INX

Increment the pointer

CPX

#DIN4+1 Has the last byte been transferred/exchanged?

BNE

TRFLP1

If the last byte has not been reached, then proceed to the

next byte for transfer/exchange

BSET

PORTD,Y %00100000 This sets the SS* output bit to a logic high,

de-selecting the LTC2400

PULA

Restore the A register

PULY

Restore the Y register

PULX

Restore the X register

RTS

Figure 34. This is an Example of 68HC11 Code That Captures the LTC2400’s

Conversion Results Over the SPI Serial Interface Shown in Figure 33

LTC2400CS8 数据表(PDF) 32 Page - Linear Technology

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