LTC2400CS8 datasheet(15/40 Pages) LINER

15 / 40 page

LTC2400

APPLICATIONS INFORMATION

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected on the falling edge of CS.

To select the external serial clock mode, the serial clock pin

(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is HI-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin. EOC

= 1 while a conversion is in progress and EOC = 0 if the

device is in the sleep state. Independent of CS, the device

automatically enters the low power sleep state once the

conversion is complete.

When the device is in the sleep state (EOC = 0), its

conversion result is held in an internal static shift regis-

ter. The device remains in the sleep state until the first

rising edge of SCK is seen while CS is LOW. Data is shifted

out the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 32nd rising edge of SCK. On the 32nd falling edge of

SCK, the device begins a new conversion. SDO goes HIGH

(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to HI-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first rising edge and the

32nd falling edge of SCK, see Figure 6. On the rising edge

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. This is useful for sys-

tems not requiring all 32 bits of output data, aborting an

invalid conversion cycle or synchronizing the start of a

conversion.

EOC

BIT 31

SDO

SCK

(EXTERNAL)

VCC

VREF

SCK

VIN

SDO

GND

VREF

0.1V TO VCC

VIN

–0.12VREF TO 1.12VREF

µF

2.7V TO 5.5V

LTC2400

TEST EOC

MSB

SUB LSB

EXR

SIG

BIT 0

LSB

BIT 4

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

2400 F05

CONVERSION

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

Hi-Z

VCC

TEST EOC

Figure 5. External Serial Clock, Single Cycle Operation

LTC2400CS8 数据表(PDF) 15 Page - Linear Technology

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