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MAX500AMLP 数据表(PDF) 1 Page - Maxim Integrated Products |
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MAX500AMLP 数据表(HTML) 1 Page - Maxim Integrated Products |
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1 / 12 page ![]() For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 _______________General Description The MAX500 is a quad, 8-bit, voltage-output digital-to- analog converter (DAC) with a cascadable serial inter- face. The IC includes four output buffer amplifiers and input logic for an easy-to-use, two- or three-wire serial interface. In a system with several MAX500s, only one serial data line is required to load all the DACs by cas- cading them. The MAX500 contains double-buffered logic and a 10-bit shift register that allows all four DACs to be updated simultaneously using one control signal. There are three reference inputs so the range of two of the DACs can be independently set while the other two DACs track each other. The MAX500 achieves 8-bit performance over the full operating temperature range without external trimming. ________________________Applications Minimum Component Count Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment ____________________________Features o Buffered Voltage Outputs o Double-Buffered Digital Inputs o Microprocessor and TTL/CMOS Compatible o Requires No External Adjustments o Two- or Three-Wire Cascadable Serial Interface o 16-Pin DIP/SO Package and 20-Pin LCC o Operates from Single or Dual Supplies ______________Ordering Information CMOS, Quad, Serial-Interface 8-Bit DAC ________________________________________________________________ Maxim Integrated Products 1 TOP VIEW 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VOUTC VOUTD VDD VREFC VREFA/B VSS VOUTA VOUTB MAX500 VREFD SRO SCL LOAD SDA LDAC DGND AGND DIP/SO _________________Pin Configurations MAX500 VOUTA DAC A DAC B DAC C DAC D VREFC VREFA/B DAC REG A INPUT REG A DAC REG B INPUT REG B DAC REG C INPUT REG C DAC REG D INPUT REG D 10/11- BIT SHIFT REGISTER CONTROL LOGIC LOAD SCL SDA VOUTB VOUTC VOUTD SRO VDD DGND VSS AGND VREFD LDAC ________________Functional Diagram 19-1016; Rev 2; 2/96 PART MAX500ACPE MAX500BCPE MAX500ACWE 0°C to +70°C 0°C to +70°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 Wide SO MAX500BCWE 0°C to +70°C 16 Wide SO MAX500BC/D 0°C to +70°C Dice* MAX500AEPE -40°C to +85°C 16 Plastic DIP MAX500BEPE -40°C to +85°C 16 Plastic DIP MAX500AEWE -40°C to +85°C 16 Wide SO MAX500BEWE -40°C to +85°C 16 Wide SO MAX500AEJE -40°C to +85°C 16 CERDIP MAX500BEJE -40°C to +85°C 16 CERDIP MAX500AMJE -55°C to +125°C 16 CERDIP MAX500BMJE -55°C to +125°C 16 CERDIP ERROR (LSB) ±1 ±2 ±1 ±2 ±2 ±1 ±2 ±1 ±2 ±1 ±2 ±1 ±2 *Contact factory for dice specifications. Pin Configurations continued on last page. MAX500AMLP -55°C to +125°C 20 LCC ±1 MAX500BMLP -55°C to +125°C 20 LCC ±2 |
类似零件编号 - MAX500AMLP |
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类似说明 - MAX500AMLP |
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