MAX500AMLP datasheet(5/12 Pages) MAXIM

5 / 12 page

CMOS, Quad, Serial-Interface

8-Bit DAC

_______________________________________________________________________________________

OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE

VOUT (V)

VSS = -5V

RO ≅ 200Ω

VSS = 0V

-6

SUPPLY CURRENT

vs. TEMPERATURE

-4

TEMPERATURE (°C)

-2

-55

125

-25

100

IDD

ISS

1.5

-2.0

ZERO-CODE ERROR

vs. TEMPERATURE

-1.5

1.0

TEMPERATURE (°C)

0.0

-1.0

0.5

-0.5

2.0

-55

125

-25

100

VSS = -5V

VOUTA

VOUTB

VOUTC

VOUTD

____________________________Typical Operating Characteristics (continued)

_______________Detailed Description

The MAX500 has four matched voltage-output digital-to-

analog converters (DACs). The DACs are “inverted”

R-2R ladder networks which convert 8 digital bits into

equivalent analog output voltages in proportion to the

applied reference voltage(s). Two DACs in the MAX500

have a separate reference input while the other two

DACs share one reference input. A simplified circuit

diagram of one of the four DACs is provided in Figure 1.

VREF Input

The voltage at the VREF pins (pins 4, 12, and 13) sets

the full-scale output of the DAC. The input impedance

of the VREF inputs is code dependent. The lowest

value, approximately 11k

Ω (5.5kΩ for VREFA/B), occurs

when the input code is 01010101. The maximum value

of infinity occurs when the input code is 00000000.

Because the input resistance at VREF is code depen-

dent, the DAC’s reference sources should have an out-

put impedance of no more than 20

Ω (no more than

Ω for VREFA/B). The input capacitance at VREF is

also code dependent and typically varies from 15pF to

35pF (30pF to 70pF for VREFA/B). VOUTA, VOUTB,

VOUTC, and VOUTD can be represented by a digitally

programmable voltage source as:

VOUT = Nb x VREF / 256

where Nb is the numeric value of the DAC’s binary

input code.

Output Buffer Amplifiers

All voltage outputs are internally buffered by precision

unity-gain followers, which slew at greater than 3V/µs.

When driving 2k

Ω in parallel with 100pF with a full-scale

transition (0V to +10V or +10V to 0V), the output settles

to ±1/2LSB in less than 4µs. The buffers will also drive

Ω in parallel with 500pF to 10V levels without oscilla-

tion. Typical dynamic response and settling perfor-

mance of the MAX500 is shown in Figures 2 and 3.

A simplified circuit diagram of an output buffer is

shown in Figure 4. Input common-mode range to

AGND is provided by a PMOS input structure. The out-

put circuitry incorporates a pull-down circuit to actively

drive VOUT to within +15mV of the negative supply

(VSS). The buffer circuitry allows each DAC output to

VREF

AGND

VOUT

DB0

DB5

DB6

DB7

DB0

DB5

DB6

DB7

…

Figure 1. Simplified DAC Circuit Diagram

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