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UTDA8024 数据表(PDF) 9 Page - Unisonic Technologies

部件名 UTDA8024
功能描述  IC CARD INTERFACE
PDF  15 Pages
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制造商  UTC [Unisonic Technologies]
网页  http://www.utc-ic.com
标志 UTC - Unisonic Technologies

UTDA8024 数据表(HTML) 9 Page - Unisonic Technologies

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UTDA8024
Preliminary
LINEAR INTEGRATED CIRCUIT
UNISONICTECHNOLOGIESCO.,LTD
9 of 15
www.unisonic.com.tw
QW-R113-014.a
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOL=200µA
0
0.2
V
LOW-Level Output Voltage
VOL
IOL=20mA (Current Limit)
VCC-0.4
VCC
V
IOH=-200µA
0.9VCC
VCC
V
HIGH-Level Output Voltage
VOH
IOH=-20mA (Current Limit)
0
0.4
V
Rise Time
tr
CL=100pF, VCC=5 or 3V
0.1
µs
Fall Time
tf
CL=100pF, VCC=5 or 3V
0.1
µs
Clock output to card reader (pin CLK)
No Load
0
0.1
V
Output Voltage
Vo(inactive) Inactive Mode
Io(inactive)=1mA
0
0.3
V
Output Current
Io(inactive)
CLK Inactive, Pin Grounded
0
-1
mA
IOL=200µA
0
0.3
V
LOW-Level Output Voltage
VOL
IOL=70mA (Current Limit)
VCC-0.4
VCC
V
IOH=-200µA
0.9VCC
VCC
V
HIGH-Level Output Voltage
VOH
IOLH=-70mA (Current Limit)
0
0.4
V
Rise Time
tr
CL=30pF, Note 5
16
ns
Fall Time
tf
CL=30pF, Note 5
16
ns
Duty Factor (Except for fXTAL)
δ
CL=30pF, Note 5
45
55
%
Slew Rate
SR
Slew Up or Down, CL=30pF
0.2
V/ns
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V) (Note 6)
LOW-Level Input Voltage
VIL
-0.3
+0.3VDD
V
HIGH-Level Input Voltage
VIH
0.7VDD
VDD+0.3
V
LOW-Level Input Leakage Current
LIL
I
0<VIL<VDD
1
µA
HIGH-Level Input Leakage Current
LIH
I
0<VIH<VDD
1
µA
Card presence inputs (pins PRES and PRES) (Note 7)
LOW-Level Input Voltage
VIL
-0.3
+0.3VDD
V
HIGH-Level Input Voltage
VIH
0.7VDD
VDD+0.3
V
LOW-Level Input Leakage Current
LIL
I
0<VIL<VDD
5
µA
HIGH-Level Input Leakage Current
LIH
I
0<VIH<VDD
5
µA
Interrupt output (pin OFF; NMOS drain with integrated 20kΩ pull-up resistor to VDD)
LOW-Level Output Voltage
VOL
IOL=2mA
0
0.3
V
HIGH-Level Output Voltage
VOH
IOH=-15µA
0.75VDD
V
Integrated Pull-Up Resistor
Rpu
20kΩ Pull-Up Resistor to VDD
16
20
24
kΩ
Protection and limitation
Shutdown and Limitation Current
pin VCC
)
sd
(
CC
I
130
150
mA
Limitation Current Pins I/O, AUX1
and AUX2
II/O(lim)
-15
+15
mA
Limitation Current Pin CLK
ICLK(lim)
-70
+70
mA
Limitation Current Pin RST
IRST(lim)
-20
+20
mA
Shut-Down Temperature
Tsd
150
°C
Timing
Activation Time
tact
see Fig.1
50
220
µs
Deactivation Time
tde
see Fig.3
50
80
100
µs
Start of the Window for Sending
CLK to the Card
t3
see Fig.1&2
50
130
µs
End of the Window for Sending
CLK to the Card
t5
see Fig.1&2
140
220
µs
Debounce Time Pins PRES
And PRES
tdebounce
see Fig.4
5
8
11
ms



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