93LC66A/B

© 1997 Microchip Technology Inc.

Preliminary

DS21209A-page 5

3.4

ERASE

The ERASE instruction forces all data bits of the spec-

ified address to the logical “1” state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed programming

cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

ming is still in progress. DO at logical “1” indicates that

the register at the specified address has been erased

and the device is ready for another instruction.

3.5

Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical “1” state. The ERAL cycle

is identical to the ERASE cycle except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the falling edge of the CS. Clocking of

the CLK pin is not necessary after the device has

entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

plete.

FIGURE 3-2:

ERASE TIMING

FIGURE 3-3:

ERAL TIMING

CS

CLK

DI

DO

CHECK STATUS

1

1

1

•••

A0

BUSY

READY

HIGH-Z

HIGH-Z

CS

CLK

DI

DO

CHECK STATUS

1

0

0

1

0

X

•••

X

BUSY

READY

HIGH-Z

HIGH-Z

Guaranteed at Vcc = 4.5V to +6.0V.