NOIP1FN016KA-GDI datasheet(17/87 Pages) ONSEMI

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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA

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Sensor States

The sensor can be in five different states:

Power-off

In this state, the sensor is inactive. All power supplies are

down and the power dissipation is zero.

Standby (1)

The registers below address 40 can be configured.

Standby (2)

In this standby state all SPI registers are active, meaning

that all SPI registers can be accessed for read and write

operations. All other blocks are disabled.

Note: An Intermediate Standby state is traversed after a

hard reset. In this state the sensor contains the default

configurations. Uploads of reserved registers are required to

traverse to the Standby (2) state

Idle

In the idle state, all sensor clocks are running and all

blocks are enabled, except the sequencer block. The sensor

is ready to start grabbing images as soon as the sequencer

block is enabled.

Running

In running state, the sensor is enabled and grabbing

images. The sensor can be operated in different global

master/slave modes.

User Actions: Power Up Functional Mode Sequences

Power-up Sequence

Figure 17 shows the power-up timing of the sensor. Apply

all power supplies in the order shown in the figure. It is

important to comply with the described sequence. Any other

supply ramping sequence may lead to high current peaks

and, as a consequence, a failure of the sensor power up.

The clock input should start running when all supplies are

stabilized. Note that before starting the clock, the LVDS

output channel multiplexing (32, 16, 8 or 4), by connecting

pins F24/F25 (muxmode0/1), should be set to the correct

supply as described in Table 31 and Table 28.

When the clock frequency is stable, the reset_n signal

can be de−asserted. After a wait period of 10

ms, the power

up sequence is finished and the first SPI upload can be

initiated.

Figure 17. Power−up Procedure

reset_n

vddd_18

vddd_33

vdda_33

LVDS clock

other supplies

vdd_casc

> 10us

NOTE:

vdd_casc should come up prior to vdd_resfd,

vdd_trans, vdd_calib and vdd_sel.

Enable Clock Management

The ’Enable Clock Management’ action configures the

clock management blocks in a pre−defined way. The

required uploads are listed in Table 6.

Table 6. ENABLE CLOCK MANAGEMENT REGISTER

UPLOAD

Upload #

Address

Data

Description

0x0000

Monochrome

0x0001

Color

0x0001

Enable Logic Blocks

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