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NOIP1FN016KA-GDI 数据表(PDF) 26 Page - ON Semiconductor |
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NOIP1FN016KA-GDI 数据表(HTML) 26 Page - ON Semiconductor |
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26 / 87 page ![]() NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA www.onsemi.com 26 Table 19. SPI TIMING REQUIREMENTS Group Addresses Description Units tsck sck clock period 100 (*) ns tsssck ss_n low to sck rising edge tsck ns tsckss sck falling edge to ss_n high tsck ns ts_mosi Required setup time for mosi 20 ns th_mosi Required hold time for mosi 20 ns ts_miso Setup time for miso tsck/2-10 ns th_miso Hold time for miso tsck/2-20 ns tspi Minimal time between two consecutive SPI accesses (not shown in figure) 2 x tsck ns *Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock). tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions. |
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