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AX88140AP 数据表(PDF) 21 Page - ASIX Electronics Corporation |
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AX88140AP 数据表(HTML) 21 Page - ASIX Electronics Corporation |
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21 / 46 page ![]() AX88140A PRELIMINARY ASIX ELECTRONICS CORPORATION 21 4.2 Host REGs 4.2.1 Bus Mode Register (REG0) FIELD R/W/C DESCRIPTION 31:22 - RESERVED 21 R/W RML - Read Multiple When set, the AX88140A supports the memory-read-multiple command on the PCI bus. This bus command is used in memory read bursts with more than one longword. When reset, the AX88140A uses memory-read command in all its memory read accesses on the PCI bus. 20 R/W DBO - Descriptor Byte Ordering Mode When set, the AX88140A operates in big edian ordering mode for descriptors only. When reset, the AX88140A operates in little endian mode. 19:14 - Reserved.--Written as “0” for future compatibility concern. 13:8 R/W PBL - Programmable Burst Length Indicates the maximum number of longwords to be transfered in one DMA transaction. If reset, the ax88140a burst is limited only by the amount of data stored in the receive FIFO (at least 16 longword), or by the amount of free space in the transmit FIFO (at least 16 longword) before issuing a bus request. The PBL can be programmed with permissible values 0,1,2,4,8,16, or 32. After reset, the PBL default value is 0. 7 R/W BLE - Big/Little Endian When set, the AX88140A operates in big endian byte ordering mode. When reset, the AX88140A operates in little endian byte ordering mode. Big endian is applicable only for data buffer 6:2 - RESERVED 1 R/W BAR - Bus Arbitration Selects the internal bus arbitration between the receive and transmit processes. When set, a round robin arbitration scheme is applied resulting in equal sharing between processes. When reset, the receive process has priority over the transmit process, unless the ax88140a is currently transmitting. 0 R/W SWR - Software Reset When set, the AX88140A resets all internal hardware with the exception of the configuration area and also, it does not change the port select setting (REG6<18>). Software reset does not affect the configuration area. Tab - 15 REG0 Bus Mode Register Description 4.2.2 Transmit Poll Demand (REG1) FIELD R/W DESCRIPTION 31:0 W TPD - Transmit Poll Demand When written with any value, the AX88140A checks for frames to be transmitted. If no descriptor is available, the transmit process returns to the suspended states and REG5<2> is asserted. If the descriptor is available the transmit process resumes. Tab - 16 REG1 Transmit Poll Demand Register Description |
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