ADP2389/ADP2390

Data Sheet

Rev. 0 | Page 20 of 23

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good printed circuit board (PCB) layout is essential for obtaining

the best performance from the ADP2389/ADP2390. Poor PCB

layout can degrade the output regulation, as well as the EMI and

electromagnetic compatibility (EMC) performance. Figure 34

shows an example of a good PCB layout for the ADP2389/

ADP2390. For optimum layout, refer to the following guidelines:



Use separate analog ground planes and power ground

planes. Connect the ground reference of sensitive analog

circuitry, such as output voltage divider components, to the

analog ground. In addition, connect the ground reference

of power components, such as input and output capacitors,

to power ground. Connect both ground planes to the

exposed GND pad of the ADP2389/ADP2390.



Place the input capacitor, the inductor, and the output

capacitor as close as possible to the IC, and use short traces.



Ensure that the high current loop traces are as short and as

wide as possible. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. To accomplish this, ensure that the input and output

capacitors share a common power ground plane.

In addition, ensure that the high current path from the power

ground plane through the inductor and output capacitor

back to the power ground plane is as short as possible by

tying the PGND pins of the ADP2389/ADP2390 to the

PGND plane as close as possible to the input and output

capacitors.



Connect the exposed GND pad of the ADP2389/ADP2390

to a large, external copper ground plane to maximize its power

dissipation capability and minimize junction temperature. In

addition, connect the exposed SW pad to the SW pins of the

ADP2389/ADP2390, using short, wide traces, or connect

the exposed SW pad to a large copper plane of the switching

node for high current flow to reduce thermal resistance.



Place the feedback resistor divider network as close as

possible to the FB pin to prevent noise pickup. Minimize

the length of the trace that connects the top of the feedback

resistor divider to the output while keeping the trace away

from the high current traces and the switching node to

avoid noise pickup. To reduce noise pickup further, place

an analog ground plane on either side of the FB trace and

ensure that the trace is as short as possible to reduce the

parasitic capacitance pickup.

Figure 33. High Current Path in the PCB Circuit

BST

FB

COMP

PGOOD

GND

VREG

RT

ILIM

FTW

SS

L

SW

PGND

EN

PVIN

VIN

ADP2389/

ADP2390

NOTES

1. ITEMS IN GRAY INDICATES HIGH CURRENT.