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USB4604 数据表(PDF) 45 Page - Microchip Technology

部件名 USB4604
功能描述  USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
PDF  62 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB4604 数据表(HTML) 45 Page - Microchip Technology

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USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
Datasheet
 2014 Microchip Technology Inc.
DS00001716A-page 45
8.2
SOF Clock Output
The USB4604 provides an 8Khz clock output synchronized to the USB host SOFs. The SOF output is
generated from the previous SOF packet on the USB line. The device includes an internal free running
frame counter to generate internal start of frame and end of frame events. The internal counter is re-
synchronized every time a successful packet is received and decoded. The internal counter is
advanced to compensate for the packet decode time. If the incoming SOF jitters early or late, the jitter
will be visible in the next frame SOF output clock rising edge.
If one or two SOFs are missing, the SOF output will continue based on the internal frame counter. If
more than two SOF are missing, the SOF output signal will stop. The clock is guaranteed to stop in a
low state. When enabled or disabled, there will never be a short cycle.
Figure 8.2 SOF Output Timing
8.3
Flex Connect
This feature allows the upstream port to be swapped with downstream physical port 1. Only
downstream port 1 can be swapped physically. Using port remapping, any logical port (number
assignment) can be swapped with the upstream port (non-physical).
Flex Connect is enabled/disabled via two control bits in the Connect Configuration Register. The
FLEXCONNECT configuration bit switches the port, and EN_FLEX_MODE enables the mode.
8.3.1
Port Control
Once EN_FLEX_MODE bit is set, the functions of certain pins change, as outlined below.
If EN_FLEX_MODE is set and FLEXCONNECT is not set:
1. PRTPWR1 enters combined mode, becoming PRTPWR1/OCS1_N
2. OCS1_N becomes a don’t care
3. SUSPEND outputs ‘0’ to keep any upstream power controller off
If EN_FLEX_MODE is set and FLEXCONNECT is set:
1. The normal upstream VBUS pin becomes a don’t care
2. PRTPWR1 is forced to a ‘1’ in combined mode, keeping the port power on to the application
processor.
3. OCS1 becomes VBUS from the application processor through a GPIO
4. SUSPEND becomes PRTPWR1/OCS1_N for the port power controller for the connector port
Upstream HS USB
Internal frame
counter events
SOF (kHz)
SOF packet accepted
EOF1
EOF2
SOF
SOF packet accepted
EOF1
EOF2
SOF



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