 2014 Microchip Technology Inc.

DS00001760B-page 33

UPD1002

3.5.3

32-BYTE CACHE

There is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. Once

the SPI controller detects a jump, the base address pointer is initialized to that address. As each new sequential data

byte is fetched, the data is written into the cache, and the length is incremented. If the sequential run exceeds 32 bytes,

the base address pointer is incremented to indicate the last 32 bytes fetched. If the device does a jump, and the jump

is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access.

3.5.4

INTERFACE OPERATION TO SPI PORT WHEN NOT PERFORMING FAST READS

There is an 8-byte command buffer: SPI_CMD_BUF[7:0]; an 8-byte response buffer: SPI_RESP_BUF[7:0]; and a length

register that counts out the number of bytes: SPI_CMD_LEN. Additionally, there is a self-clearing GO bit in the SPI_CTL

Register. Once the GO bit is set, the device drops SPI_ROM_CE_N, and starts clocking. It will put out SPI_CMD_LEN

X 8 number of clocks. After the first byte, the COMMAND, has been sent out, and the SPI_ROM_DI is stored in the

SPI_RESP buffer. If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the

SPI_ROM_DO line. This mode is used for program execution out of internal RAM or ROM.

FIGURE 3-5:

SPI ROM DUAL HI-SPEED READ SEQUENCE

FIGURE 3-6:

SPI ROM INTERNALLY-CONTROLLED OPERATION

SPI_ROM_CE_N

SPI_ROM_CLK

SPI_ROM_DO

SPI_ROM_DI

8

0B

MSB

HIGH IMPEDANCE

15 16

12 3 4

05

7

6

D1

ADD.

23 24

ADD.

ADD.

X

39 40

31 32

44

47 48

51 52

55 56

59

D2

N

N+1

D3

N+2

D4

N+3

D5

N+4

MSB

MSB

D1

D2

NN+1

D3

N+2

D4

N+3

D5

N+4

MSB

43

Bits-7,5,3,1

Bits-7,5,3,1

Bits-7,5,3,1

Bits-7,5,3,1

Bits-6,4,2,0

Bits-6,4,2,0

Bits-6,4,2,0

Bits-6,4,2,0

Bits-7,5,3,1

Bits-6,4,2,0

SPI

CONTROLLER

SPI

ROM

SPI_RSP_BUF[7:0]

SPI_CMD_BUF[3:0]

SPI_CMD_LEN

CE#

CLK

SI

SO

UPD1002