 2014 Microchip Technology Inc.

DS00001760B-page 7

UPD1002

2.0

PIN DESCRIPTIONS AND CONFIGURATION

The pinouts for the package, along with system-level application diagrams, are detailed in the following section:

• 32-Pin SQFN (32-SQFN)

Note:

For a summary of the available pin combinations and their corresponding target applications, refer to

Table 1-1.

Pin descriptions are detailed in Section 2.2, "Pin Descriptions," on page 14. For details on the CFG_SEL0 and CFG_-

SEL1 Configuration Select signals, refer to Section 3.3, "Configuration Selection (CFG_SEL0/CFG_SEL1)," on

page 24.

2.1

32-Pin SQFN (32-SQFN)

2.1.1

32-SQFN PIN DIAGRAM

Note:

When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example,

RESET_N indicates that the reset signal is active low.

FIGURE 2-1:

32-SQFN PIN ASSIGNMENTS (TOP VIEW)

(Connect exposed pad to ground with a via field)

VSS

UPD1002

32-SQFN

(Top Vi ew)

Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.

*The functionality of this pin is dependent on the CFG_SEL0/CFG_SEL1 profile selection.

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CFG_SEL1

CFG_SEL0

PD_EN/PD_GOOD*

VDD33_CAP

VBUS

VSW_CAP

VTR

VDD18A_CAP

PD_DATA

PD_ID

PD_VDD18

VDDIO

IMON

VMON

VDD18_CAP

HUB_PWR_EN/VSEL2_N*