A6986F datasheet(45/72 Pages) STMICROELECTRONICS

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A6986F

Application notes

7.1

Output voltage adjustment

The error amplifier reference voltage is 0.85 V typical.

The output voltage is adjusted accordingly with Equation 41 (see Figure 36):

Equation 41

Cr1 capacitor is sometimes useful to increase the small signal phase margin (please refer to

Section 6.5: Compensation network design).

Figure 36. A6986F application circuit

7.2

Switching frequency

A resistor connected to the FSW pin features the selection of the switching frequency. The

pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is

pinstrapped and then driven floating in order to minimize the quiescent current from VIN.

Please refer toTable 6: fSW selection on page 11 to identify the pull-up / pull-down resistor

value. fSW = 250 kHz / fSW = 500 kHz preferred codifications don't require any external

resistor.

7.3

MLF pin

A resistor connected to the MLF pin features the selection of the between low noise mode /

low consumption mode and the different RST thresholds. The pinstrapping is performed at

power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven

floating in order to minimize the quiescent current from VIN.

Please refer to Table 7 on page 11, Table 8 on page 12, and Table 9 on page 12 to identify

the pull-up / pull-down resistor value. (LNM, RST threshold 93%) / (LCM, RST threshold

93%) preferred codifications don't require any external resistor.

VOUT

0.85

-------







signal GND

PWR gnd

uC RST

A6986F

VBIAS

RST

VCC

SS/INH

SYNCH

FSW

MLF

COMP

DELAY

SGND

PGND

VIN

10uF

VOUT

470nF

GND

10nF

1uF

GND

6.8uH

20uF

68nF

VIN

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