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A6986F 数据表(PDF) 49 Page - STMicroelectronics

部件名 A6986F
功能描述  38 V 1.5 A synchronous step-down switching regulator
PDF  72 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

A6986F 数据表(HTML) 49 Page - STMicroelectronics

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A6986F
Application notes
72
Multiple A6986F can be synchronized to an external frequency signal fed to the SYNCH pin.
In this case the regulator set is phased to the reference and all the devices will work with 0°
phase shift.
The frequency range of the synchronization signal is 275 kHz - 2 MHz and the minimum
pulse width is 100 nsec (see Figure 41).
Figure 41. Synchronization pulse definition
Since the slope compensation contribution that is required to prevent subharmonic
oscillations in peak current mode architecture depends on the switching frequency, it is
important to select the same oscillator frequency for all regulators (all of them operate as
SLAVE) as close as possible to the frequency of the reference signal (please refer to
Table 6: fSW selection on page 11). As a consequence all the regulators have the same
resistor value connected to the FSW pin, so the slope compensation is optimized
accordingly with the frequency of the synchronization signal. The slope compensation
contribution is latched at power-up and so fixed during the device operation.
The A6986 normally operates in MASTER mode, driving the SYNCH line at the selected
oscillator frequency as shown in Figure 42 and Figure 39.
In SLAVE mode the A6986 sets the internal oscillator at 250 kHz typ. (see Table 6 on
page 11 - first row) and drives the line accordingly.
Figure 42. A6986 synchronization driving capability
In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the
normal operation, the external master must drive the SYNCH pin with a clock signal
fSYNCHRO
100nsec min.
275kHz < fSYNCHRO < 2MHz
fSYNCHRO
100nsec min.
V
CC INT
5 mA
0.7 mA
fOSC
150nsec typ.
HIGH LEVEL
LOW LEVEL



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