SRK2001 datasheet(9/22 Pages) STMICROELECTRONICS

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DocID027367 Rev 3

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SRK2001

Operation description

The device block diagram is shown in Figure 1 on page 3. The SRK2001 can be supplied

through the VCC pin by the same converter output voltage, within a wide voltage range

(from 4.5 V to 32 V), internally clamped to VCCZ (36 V typical). An internal UVLO

(undervoltage lockout) circuit with hysteresis keeps the device switched off at supply voltage

lower than the turn-on level VCC_On, with reduced consumption. After the startup, the

operation with VCC floating (or disconnected by supply voltage) while pins DVS1, 2 are

already switching is not allowed: this in order to avoid that a dV/dt on the DVS pin may

cause a high flowing current with possible damage of the IC.

The core of the device is the control logic block, implemented by asynchronous logic: this

digital circuit generates the logic signals to the output drivers, so that the two external power

MOSFETs are switched on and off, depending on the evolution of their drain-source

voltages, sensed on the DVS-SVS pin pairs through the comparators block.

The logic that controls the driving of the two SR MOSFETs is based on two gate driver state

machines working in parallel in an interlocked way to avoid switching on both gate drivers at

the same time. A third state machine manages the transitions from the normal operation to

the sleep mode and vice versa.

5.1

Drain voltage sensing

The SRK2001 basic operation is such that each synchronous rectifier MOSFET is switched

on whenever the corresponding transformer half-winding starts conducting (i.e.: when the

MOSFET body diode, or an external diode in parallel, starts conducting) and it is then

switched off when the flowing current approaches zero. To understand the polarity and the

level of this current, the IC is provided with two pairs of pins (DVS1 - SVS1 and DVS2 -

SVS2) that sense the drain-source voltage of either MOSFET (Kelvin sensing). In order to

limit dynamic current injection in any condition, at least 100

 resistors in series to DVS1, 2

pins must be used.

Referring to the typical waveforms in Figure 5, there are three significant voltage thresholds:

the first one, VTH_A (= 1.4 V), sensitive to positive-going edges, arms the opposite gate

driver (interlock function); the second one VTH_PT (= 0.7 V), sensitive to negative-going

edges provides a pre-trigger of the gate driver; the third one VTH-ON is the (negative)

threshold that triggers the gate driver as the body diode of the SR MOSFET starts

conducting.

5.2

Turn-on

The turn-on logic is such that each SR MOSFET is switched on when the sensed drain-

source voltage goes below the VTH_ON threshold: to avoid false triggering of the gate driver,

an adaptive masking delay TD_On is introduced. This delay assumes a minimum value at the

high load and increases with decreasing load levels. The aim of TD_On is to avoid

a premature turn-on at lower load conditions, triggered by capacitive currents (due to

secondary side parasitic) and not really related to the current flowing through the body

diode.

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