Operation description

SRK2001

16/22

DocID027367 Rev 3

5.7.2

Automatic sleep mode function disabled

The EN pin is open and only a resistor is connected to the PROG pin, as indicated in

Figure 9: at the startup (with the external switch open) an internal pull-up allows the EN pin

voltage to increase above an internal threshold, where the automatic sleep mode function is

disabled and the configuration is internally stored. In this way the controller does not enter

the low consumption state when the conduction duty cycle reduces consequently to the

light-load operation.

It is worth noticing that, with automatic sleep mode function disabled, the SR controller can

still enter the low consumption mode, when it detects a half bridge converter stop

(i.e.: primary controller burst mode operation) or when the EN pin is pulled down by the user

(through a npn transistor like in Figure 9). After the primary side switching restarts or the EN

pin goes back high, the controller resumes the operation when it detects that the conduction

duty cycle has increased above the values in Table 8: the user can select the desired value

5.8

Layout guidelines

The GND pin is the return of the bias current of the device and the return for gate drive

currents: it should be routed to the common point where the source terminals of both

synchronous rectifier MOSFETs are connected. When laying out the PCB, care must be

taken in keeping the source terminals of both SR MOSFETs as close to one another as

possible and routing the trace that goes to GND separately from the load current return

path. This trace should be as short as possible and be as close to the physical source

terminals as possible. Doing the layout as more geometrically symmetrical as possible will

help make the circuit operation as much electrically symmetrical as possible.

Also drain-source voltage sensing should be done as physically close to the drain and

source terminals as possible in order to minimize the stray inductance involved by the load

current path that is in the drain-to-source voltage sensing circuit.

25%

75%

70%

60%

55%

80%

75%

65%

0%