ST-PLC-AFE datasheet(7/58 Pages) STMICROELECTRONICS

7 / 58 page

DocID028727 Rev 1

7/58

ST-PLC-AFE

General description

The ST-PLC-AFE combines a digital-to-analog converter (DAC), an adaptive gain control

(AGC), programmable filters, and a line driver on a single chip. The architecture is divided

into three primary functional blocks:

•

Power amplifier (PA)

The PA is characterized by the following features:

–

Differential or single-ended output architecture

–

1.65 A drive capability @ 14 Vpp

–

Gain of 6.9 V/V

–

PA current limiter with four programmable limits: 0.5 A, 1 A, 1.5 A, and 2.1 A

–

Integrated thermometer placed closed to the PA

•

Transmitter chain (Tx)

The Tx is characterized by the following features:

–

Can work with a 10-bit internal DAC

–

Can be driven with an external DAC through the TX_INP input pin

–

Programmable unity-gain fourth-order low-pass filter, following CENELEC bands

A, B, C, and D.

–

PGA with gains of 6 dB, 0 dB, -18 dB, and -36 dB

•

Receiver chain (Rx)

The Rx is characterized by the following features:

–

PGA1 with gains of -3 dB, 3 dB, 9 dB, and 15 dB

–

Sensitivity of 20 µVrms typical

–

Can be connected in differential or single-input mode

–

Programmable

unity-gain fourth-order low-pass filter, following CENELEC bands

A, B, C, and D.

–

Selectable high-pass filter with a 35 kHz cutoff frequency)

–

PGA2 with gains of -6 dB, 6 dB, 18 dB, and 30 dB

The ST-PLC-AFE supports other circuitry blocks, such as:

•

SPI interface for the microcontroller

•

Thermal shutdown

•

Two zero crossing detectors

ST-PLC-AFE 数据表(PDF) 7 Page - STMicroelectronics

ST-PLC-AFE 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载