5

The VHDL libraries are VITAL 3.0 compliant and the Verilog libraries are OVI 1.0 compliant. With the library capabilities Aero-

flex provides, you can use High Level Design methods to synthesize your design for simulation. Aeroflex also provides tools to

verify that your HDL design will result in successful implementations.

ADVANTAGES OF THE AEROFLEX HDL DESIGN SYSTEMS

• The Aeroflex HDL Design System gives you the freedom to use tools from Synopsys, Mentor Graphics, Cadence and other ven-

dors to help you synthesize and verify a design.

• Aeroflex's Logic Rules Checker and Tester Rules Checker allow you to verify partial or complete designs for compliance with

Aeroflex design rules.

• Aeroflex HDL Design System accepts back-annotation of timing information through SDF.

XDTSM (EXTERNAL DESIGN TRANSLATION)

Through Aeroflex's XDT services, customers can convert an existing non-Aeroflex design to Aeroflex's UT130nHBD platform for

increased power/speed performance. The XDT capability is particularly useful for converting an FPGA to an Aeroflex radiation-

tolerant technology. The XDT translation tools convert industry standard netlist formats and 3rd party vendor libraries to Aeroflex

formats and libraries. Industry standard netlist formats supported by Aeroflex include:

• VHDL

• Verilog HDL

• FPGA source files (Actel, Altera, Xilinx)

• EDIF

• Third-party netlists supported by Synopsys

RTL Development

70% Done

85% Done

95-100% Don e

RTL

Synthesis

DC Ultra

Netli st

ICC

Floor pl an &

Gl obal Route

LEF/DEF

RTL

Synthesis

DCUltra

Netl ist

ICC

Place & Route

Reviews

Analysis / Fi xing

(DC Graphical & ICC-DP)

Floor Planning

Synthesis / P&R Scripts

RTL

Synthesis

DC Ultra

Netli st

ICC

Place & Route

Sign-off

& Tape out

Analysi s / Fixing

(DC Graphi cal & ICC-DP )

Final Flow

Liberty

FRAM

TLU-Pl us

Figure 1: Design Plan