2

(All supplies referenced to ground)

Note:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation

of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

2.The recommended "power-on" sequences is VDDQ voltage supply applied first, followed by the VDDIO voltage supply. The recommended "power-off" sequence

is the reverse. Remove VDDIO voltage supply, followed by removing VDDQ voltage supply.

RECOMMENDED OPERATING CONDITIONS

Table 1: Library Overview

CHARACTRISTICS

VALUE

Technology

TSMC 130G - 130nm Bulk CMOS, 8 metal layers

Logic Density

86K gates/mm2 = ~15M gates

Supply Voltages

3.3V, 2.5V (planned) & 1.8V I/O; 1.2V core

Typical Power Dissipation

~ 18nW/gate-MHz @ 1.2V

Standard Cells

~ 300 multi-VT cells (high VT, standard VT and low VT)

Intrinsic Gate Delay (na02nd2)

50ps

Fastest Core Frequency

570 MHz (10 levels of logic)

I/O's

3.3V, 2.5V (planned); 4, 8, 12, 24mA outputs; LVCMOS, LVTTL,

Schmitt trigger; bidirectional, programmable, configurable pull up/

down

Memories

Single & Dual-port SRAM & Register file compiler

Macros

HSTL (250MHz), LVDS (400Mbps), PLL's (100-500MHz), SerDes

(3.125Gbps - in development)

Rated Temp Range

-55°C to 125°C

ESD (Human Body Model)

1kV

Packaging Options

Wirebond: CQFP, CCGA, CBGA. Flip Chip (in development)

SYMBOL

PARAMETER

LIMITS

2

I/ODC supply voltage

-0.3V to 3.3V +30%

2

Core DC supply voltage

-0.3V to 1.2V + 30%

Storage temperature

-65

°C to +150°C

Maximum junction temperature

+150

°C

Latchup immunity

DC input current

Lead temperature (soldering 5 sec)

+300

°C

SYMBOL

PARAMETER

LIMITS

IO DC supply voltage

3.0V + 0.3

Core DC supply voltage

1.2V+ 0.1