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Data from the wafer-level testing can provide rapid feedback to the fabrication process, as well as establish the reliability perfor-

mance of the product before it is packaged and shipped.

RADIATION TOLERANCE

Aeroflex incorporates radiation-tolerance techniques in process design, design rules, array design, power distribution and library

element design. All key radiation-tolerance process parameters are controlled and monitored using statistical methods and in-line

testing (Table 3).

Notes:

1.Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019.

2.TID data measured at 1.35V core/3.6V I/ O VDDIO. All post radiation values measured at 25°C.

3.SEU limit based on standard evaluation circuit at 1.1V core/3.0V I/ O VDDIO 25°C condition.

4.SEU-hard flip-flop cell. Non-hard flip-flop typical is 5x10-8.

5.SEL data measured at 1.3V core/3.6V I/ O VDDIO and 125°C.

Intel is a registered trademark of Intel Corporation

Mentor, Mentor Graphics, FastScan, FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation

Sun is a registered trademark of Sun Microsystems, Inc.

Synopsys, Design Compiler, VHDL Compiler, HDL Compiler, Te

Table 3: Radiation Hardness

PARAMETER

RADIATION

TOLERANCE

NOTES

Total ionizing dose

100-300 krad(Si)

1,2

Single event upset (SEU)

3,4

Single event latchup (SEL)

Latchup immune to LET =

115 MeV/cm2/mg

5