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STA016T 数据表(PDF) 16 Page - STMicroelectronics |
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STA016T 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 45 page ![]() STA016T 16/45 Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz PLL_AUDIO_XDIV_192 : Address : 0xDF (223) Type : RW - DEC Software Reset : 3 Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz PLL_AUDIO_MDIV_192 : Address : 0xE0 (224) Type : RW - DEC Software Reset : 12 Description : This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz PLL_AUDIO_PEL_176 : Address : 0xE1 (225) Type : RW - DEC Software Reset : 54 Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – fact == 256 – external crystal provide a CRYCK running at 14.31818 MHz PLL_AUDIO_PEH_176 : Address : 0xE2 (226) Type : RW - DEC Software Reset : 118 Description : This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz PLL_AUDIO_NDIV_176 : Address : 0xE3 (227) Type : RW - DEC Software Reset : 0 Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 |
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