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STA016T 数据表(PDF) 23 Page - STMicroelectronics

部件名 STA016T
功能描述  MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM
PDF  45 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA016T 数据表(HTML) 23 Page - STMicroelectronics

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STA016T
I_AUDIO_CONFIG_3 :
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_4 register description..
I_AUDIO_CONFIG_4 :
Address : 0x5E (94)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
I_AUDIO_CONFIG_5:
Address : 0x5F (95)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description.
I_AUDIO_CONFIG_6 :
Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
I_AUDIO_CONFIG_7 :
Address : 0x61 (97)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
CF11
Bit to select the reference clock used to
generate BCK if clocks are in output
(CF2=1 & CF5=1). Otherwise this bit is
useless.
0 : SYSCK
1 : PCMCK
CF12
Reserved : to be set to 1
CF13
Reserved : to be set to 1
CF14
Reserved : to be set to 0
CF15
Reserved : to be set to 0
b7
b6
b5
b4
b3
b2
b1
b0
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
b7
b6
b5
b4
b3
b2
b1
b0
LR15 LR14 LR13 LR12 LR11 LR10
LR9
LR8
Bit fields
Comment
LR[5:0]
Length-1 of phase 1 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
Bit
Comment
LR[11:6]
Length-1 of phase 2 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
LR[15:12]
Reserved : to be set to 0
b7
b6
b5
b4
b3
b2
b1
b0
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
b7
b6
b5
b4
b3
b2
b1
b0
MA15 MA14 MA13 MA12 MA11 MA10 MA9
MA8
b7
b6
b5
b4
b3
b2
b1
b0
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
Bit fields
Comment



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